DRAFT
EE/CS/MedE 175

Digital Circuits Analysis and Design with Complete VHDL and RTL Approach

9 units (3-6-0)  |  third term
Prerequisites: medium to advanced knowledge of digital electronics.
A careful balance between synthesis and analysis in the development of digital circuits plus a truly complete coverage of the VHDL language. The RTL (register transfer level) approach. Study of FPGA devices and comparison to ASIC alternatives. Tutorials of software and hardware tools employed in the course. VHDL infrastructure, including lexical elements, data types, operators, attributes, and complex data structures. Detailed review of combinational circuits followed by full VHDL coverage for combinational circuits plus recommended design practices. Detailed review of sequential circuits followed by full VHDL coverage for sequential circuits plus recommended design practices. Detailed review of state machines followed by full VHDL coverage and recommended design practices. Construction of VHDL libraries. Hierarchical design and practice on the hard task of project splitting. Automated simulation using VHDL testbenches. Designs are implemented in state-of-the-art FPGA boards. Offered 2021-2022.
Instructor: Pedroni

Please Note

The online version of the Caltech Catalog is provided as a convenience; however, the printed version is the only authoritative source of information about course offerings, option requirements, graduation requirements, and other important topics.