IST Lunch Bunch

Tuesday January 20, 2015 12:00 PM

Multicore in Space, NASA and AFRL Invest in the Future of Flight Computing

Speaker: Richard Doyle, Project Manager, High Performance Spaceflight Computing, Jet Propulsion Laboratory
Location: Annenberg 105

Onboard computing can be aptly viewed as a "technology multiplier" for space missions, in that advances provide broad improvements in flight functions and capabilities, and enable new flight capabilities and mission scenarios, increasing science and exploration return.

To sharpen understanding of the gap between the current state of the practice in flight computing and the near- to mid-term needs of NASA missions, a multi-center NASA team conducted a High Performance Spaceflight Computing (HPSC) formulation study, funded by the NASA Space Technology Game Changing Development Program.

To answer the question: "What are the paradigm-shifting NASA space-based applications that drive flight computing?" a series of workshops was conducted with personnel from NASA Johnson Space Center (JSC), NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL).  These scientists and engineers identified use cases from the future NASA mission set, both robotic and human, that require onboard high performance computing. 

To answer the related question: "What are the requirements imposed on flight computing by these applications?" engineers and mission personnel characterized for each use case:  the nature of the computing, the environment, the criticality of the application, the system constraints, and the computing system and processor chip requirements.

As NASA's HPSC study proceeded, AFRL and NASA identified significant overlap in future requirements and common interest in future flight computing.  An agency-level partnership emerged, which is manifesting through joint investment program termed Next-Generation Space Processing (NGSP).

Under a Study Phase, AFRL and NASA issued awards to develop hardware architecture designs for the future flight computing system.  NASA is also developing a set of benchmarks based on the NASA applications.  Some benchmarks capture the usual performance needs but others benchmarks are for the purpose of evaluating certain system-level properties of the vendor-offered designs, such as support for energy management and fault tolerance.

The hardware architecture designs are being evaluated, and, assuming a viable departure point, a Development Phase will follow in FY16-18, to culminate in a flight computing system with bundled operating system, software development environment, and middleware to exploit architectural features for the benefit of the identified applications.  NASA and AFRL intend to continue in partnership through the Development Phase, and are seeking additional programmatic partners for this national-level capability investment.

Series IST Lunch Bunch

Contact: Christine Ortega at 626.395.2076 cortega@caltech.edu