Caltech Mixed-Signal, RF and Microwave Seminar

Friday October 11, 2013 4:00 PM

Design, Test, and EDA Research for 3D ICs at GTCAD Laboratory

Speaker: Sung Kyu Lim, School of Electrical and Computer Engineering, Georgia Institute of Technology
Location: Moore B280

Abstract: This talk presents an overview of 3D IC research at the Georgia Tech ComputerAided Design (GTCAD) laboratory. First, we present 3DMAPS (3D Massively Parallel Processor with Stacked Memory) V1 processor, a logic+memory 2tier 3D IC that features 64 generalpurpose processor cores and SRAM. This is arguably the first generalpurpose manycore 3D processor ever developed in academia and fully tested using real applications. This 3D processor achieves up to 64GB/s memory bandwidth while consuming 4W power. This work is presented at the IEEE International SolidState Circuits Conference (2012). We also present 3DMAPS V2, a 5tier extension of V1 that features 128 cores and 256MB wideI/O 3D DRAM. We discuss the entire chip development spectrum (except manufacturing): architecture and verification, programming, design and signoff analysis, package/board design, and testing. Moreover, we discuss our RTLtoGDSII CAD tool flow that is based on various 2D IC commercial tools and our plugins to handle 3D ICs.

Second, we investigate the multiphysics (= thermoelectromechanical) reliability issues in throughsiliconvia (TSV)based 3D ICs and develop EDA solutions. We study how to model these complex phenomena, apply them to analyze the reliability of largescale 3D circuits, and develop fullchip design methods to mitigate the issues. Third, we investigate the design benefits and challenges for monolithic 3D ICs, considered by many as the future of 3D ICs, where the individual tiers are "grown" on top of each other, instead of being "bonded". The biggest benefit is the nanoscale intertier vias that are a few orders of magnitude smaller than TSVs. Monolithic 3D IC enables ultrafinegrained 3D integration, which finds numerous applications in logic and memory systems. Lastly, we present various low power design methods developed based on 3D IC implementations of ultra SPARC T2 processor (open source commercial processor with 500million transistor) and 28nm PDK.

 

 

Series Mixed-Signal, RF, and Microwave Seminar

Contact: Michelle Chen mchen1@caltech.edu
For more information visit: http://www.ee2.caltech.edu/calendar/mixed-fall.html