Caltech Mixed-Signal, RF and Microwave Seminar
Design, Test, and EDA Research for 3D ICs at GTCAD Laboratory
Abstract: This talk presents an overview of 3D IC research at the Georgia Tech Computer‐Aided Design (GTCAD) laboratory. First, we present 3D‐MAPS (3D Massively Parallel Processor with Stacked Memory) V1 processor, a logic+memory 2‐tier 3D IC that features 64 general‐purpose processor cores and SRAM. This is arguably the first general‐purpose many‐core 3D processor ever developed in academia and fully tested using real applications. This 3D processor achieves up to 64GB/s memory bandwidth while consuming 4W power. This work is presented at the IEEE International Solid‐State Circuits Conference (2012). We also present 3D‐MAPS V2, a 5‐tier extension of V1 that features 128 cores and 256MB wide‐I/O 3D DRAM. We discuss the entire chip development spectrum (except manufacturing): architecture and verification, programming, design and sign‐off analysis, package/board design, and testing. Moreover, we discuss our RTL‐to‐GDSII CAD tool flow that is based on various 2D IC commercial tools and our plug‐ins to handle 3D ICs.
Second, we investigate the multi‐physics (= thermo‐electro‐mechanical) reliability issues in through‐silicon‐via (TSV)‐based 3D ICs and develop EDA solutions. We study how to model these complex phenomena, apply them to analyze the reliability of large‐scale 3D circuits, and develop full‐chip design methods to mitigate the issues. Third, we investigate the design benefits and challenges for monolithic 3D ICs, considered by many as the future of 3D ICs, where the individual tiers are "grown" on top of each other, instead of being "bonded". The biggest benefit is the nano‐scale inter‐tier vias that are a few orders of magnitude smaller than TSVs. Monolithic 3D IC enables ultra‐fine‐grained 3D integration, which finds numerous applications in logic and memory systems. Lastly, we present various low power design methods developed based on 3D IC implementations of ultra SPARC T2 processor (open source commercial processor with 500‐million transistor) and 28nm PDK.
Contact: Michelle Chen firstname.lastname@example.org
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