Mixed-Signal, RF, and Microwave Seminar

Friday May 2, 2008 4:00 PM

P3: Parallel-Arrayed, Power-Optimal, Process-Calibrating, Interconnect Circuits for Future Multi-Core Computing

Speaker: Patrick Chiang, Oregon State University
Location: Moore B280
"P3: Parallel-Arrayed, Power-Optimal, Process-Calibrating, Interconnect Circuits for Future Multi-Core Computing," PPatrick Chiang, assistant professor of electrical and computer engineering, Oregon State University.
Series Mixed-Signal, RF, and Microwave Seminar