IST Lunch Bunch
November 29, 2011
Design and Analysis of High-Performance Compressed Sensing Receivers
The Shannon-Nyquist sampling theorem is implicit in the design of most conventional signal-acquisition systems. As contemporary/emerging applications demand increased bandwidth and data resolution, realizing an ADC that meets system requirements can become a serious performance bottleneck. This is due to the unfavorable scaling relationship that exists between power consumption and sampling-rate. Recently, results from the field of compressed sensing have provided an alternative mean to realize signal acquisition systems. Specifically, compressed sensing enables sub-Nyquist rate signal acquisition provided the acquired signal is sparse in the sense that it depends on a number of degrees of freedom much lower than its bandwidth suggests.
In this talk, details of design and implementation of integrated frontends for compressed sensing receivers are discussed. In particular, we will focus on challenges and requirements of such receivers in deep sub-micron CMOS technologies. We will also present simulation and measurement results that examine the robustness of compressed sensingbased receivers against noise, clock jitter, mismatch and nonlinearities. Our design methodology and parameter optimization will be explained via simulations that include precise hardware and noise models. Finally, measurement results from a fully integrated compressed sensingbased receiver in 90nm CMOS technology that achieves more than 2.0 GHz of instantaneous bandwidth with 12.5x sub-Nyquist rate will be presented.
IST Lunch Bunch